Low Latency & High Throughput Wireless-NoC Architecture for Manycore Processors

Published in IEEE Xplore, 2018

Abstract: Network on chip (NoC) is a communication subsystem on an IC, typically between intellectual property (IP) cores in a system on a chip (SoC). NoC helps to accomplish greater throughput in multi-core chips. Communication among the cores is established via routers interfaced to each core. The communication unit across the core are flits that pass through routers to reach the destination. It replaces dedicated point to point wiring between cores on a chip and increases scalability. But as the cores grow in number, the communication between two distantly placed cores becomes cumbersome. Proposed paper describes a technique called Adaptive WiNoC to reduce traffic at wireless routers by checking the buffer occupancy at the wireless routers, placing the flits in some other routers when the wireless routers are full and introducing output queue in the wireless router.

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